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Principles of Verifiable Rtl Design:; a functional coding style supporting verification processes in Verilog
de Bening, Lionel; Foster, Harry
- Usado
- Tapa dura
- First
- Estado
- Faint rubbed fold to spine head & foot & folds, barely rubbed corners, else near fine(+).
- ISBN 10
- 0792377885
- ISBN 13
- 9780792377887
- Librería
-
Oakland, California, United States
Formas de pago aceptadas
Sobre este artículo
Norwell, Mass: Kluwer Academic Publishers, 2000. First edition (presumed; no earlier dates stated). Hardcover. Faint rubbed fold to spine head & foot & folds, barely rubbed corners, else near fine(+).. Purple octavo; xvii, 253 p, b&w illus; 24 cm. Contents: Register Transfer Level --; What is It? --; Verifiable RTL --; Applying Design Discipline --; The Verification Process --; Specification Design Decomposition --; High-Level Design Requirements --; Block-Level Specification and Design --; RTL Implementation --; Synthesis and Physical Design --; Functional Test Strategies --; Deterministic or Directed Test --; Random Test --; Transaction Analyzer Verification --; Chip Initialization Verification --; Synthesizable Testbench --; Transformation Test Strategies --; Coverage, Events and Assertions --; Coverage --; Ad-hoc Metrics --; Programming Code Metrics --; State Machine and Arc Coverage Metrics --; User Defined Metrics --; Fault Coverage Metrics --; Regression Analysis and Test Suite Optimization --; Event Monitors and Assertion Checkers --; Events --; Assertions --; Assertion Monitor Library Details --; Event Monitor and Assertion Checker Methodology --; Linting Strategy --; Implementation Considerations --; Event Monitor Database and Analysis --; RTL Methodology Basics --; Simple RTL Verifiable Subset --; Linting --; Linting in a design project --; Lint description --; Project Oriented --; Linting Message Examples --; Object-Based Hardware Design --; OBHD and Simulation --; OBHD and Formal Verification --; OBHD and Physical Design --; OBHD Synthesis --; OBHD Scan Chain Hookup --; A Text Macro Implementation --; RTL Logic Simulation --; Simulation History --; First Steps --; X, Z and Other States --; Function and Timing --; Gate to RTL Migration --; Acceleration and Emulation --; Language Standardization. Integrated circuits -- Very large scale integration -- Computer-aided design.
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Detalles
- Librería
- Bibliope by Calvello Books (US)
- Inventario del vendedor #
- 23856
- Título
- Principles of Verifiable Rtl Design:; a functional coding style supporting verification processes in Verilog
- Autor
- Bening, Lionel; Foster, Harry
- Formato/Encuadernación
- Tapa dura
- Estado del libro
- Usado - Faint rubbed fold to spine head & foot & folds, barely rubbed corners, else near fine(+).
- Cantidad disponible
- 1
- Edición
- First edition (presumed; no earlier dates stated)
- ISBN 10
- 0792377885
- ISBN 13
- 9780792377887
- Editorial
- Kluwer Academic Publishers
- Lugar de publicación
- Norwell, Mass
- Fecha de publicación
- 2000
- Palabras clave
- Design And Decorative Arts
Términos de venta
Bibliope by Calvello Books
Books may be placed on reserve for one week. Refunds may be issued if book is not as described and is returned in same condition as it was originally shipped, and within two weeks of order.
Sobre el vendedor
Bibliope by Calvello Books
Miembro de Biblio desde 2005
Oakland, California
Sobre Bibliope by Calvello Books
Over thirty-five years experience in the used, out-of-print and rare book trades. Selling online since 1997. WWW.BIBLIOPE.COM (formerly Calvello Books)
Glosario
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- First Edition
- In book collecting, the first edition is the earliest published form of a book. A book may have more than one first edition in...
- Spine
- The outer portion of a book which covers the actual binding. The spine usually faces outward when a book is placed on a shelf....