Logic Synthesis and Verification Algorithms Tapa blanda - 2006
de Gary D. Hachtel; Fabio Somenzi
Descripción de contraportada
In the last decade logic synthesis has gained widepsread acceptance by designers. Formal verification is now advancing along the same path. Computer aided design tools for logic synthesis and verification have become the primary instrument for coping with the ever increasing complexity of designs, and ever more stringent time-to-market constraints. Effective design must be based on thorough understanding of the capabilities, limitations, and algorithmic principles employed by these tools. In this book we provide a foundation for such understanding.
Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization.
Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.
Circuit designers and CAD tool developers alike will find Logic Synthesis and Verification Algorithms useful as an introductory and reference text. The rich collection of examples and solved problems make this book ideal for self study.
Because of its careful balance of theory and application, Logic Synthesis and Verification Algorithms will serve well as a textbook for upper division and first year graduate students in electrical and computer engineering.
Detalles
- Título Logic Synthesis and Verification Algorithms
- Autor Gary D. Hachtel; Fabio Somenzi
- Encuadernación Tapa blanda
- Edición INTERNATIONAL ED
- Páginas 564
- Volúmenes 1
- Idioma ENG
- Editorial Springer, Boulder
- Fecha de publicación February 10, 2006
- Ilustrado Sí
- Features Bibliography, Illustrated, Index, Table of Contents
- ISBN 9780387310046 / 0387310045
- Peso 1.6 libras (0.73 kg)
- Dimensiones 9.1 x 6.1 x 1.3 pulgadas (23.11 x 15.49 x 3.30 cm)
- Library of Congress subjects Computer-aided design, Logic design - Data processing
- Número de catálogo de la Librería del Congreso de EEUU 2005937330
- Dewey Decimal Code 621.395
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Logic Synthesis and Verification Algorithms
de Hachtel, Gary D.; Somenzi, Fabio
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Logic Synthesis and Verification Algorithms
de Hachtel, Gary D
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Logic Synthesis and Verification Algorithms
de Hachtel, Gary D.; Somenzi, Fabio
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- ISBN 10 / ISBN 13
- 9780387310046 / 0387310045
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San Diego, California, United States
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